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White Electronic Designs
WV3EG32M64ETSU-D3
ADVANCED*
256MB - 32Mx64 DDR SDRAM UNBUFFERED
FEATURES
Double-data-rate architecture PC2700 @ CL 2.5 Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh, (8K/64ms refresh) Serial presence detect with EEPROM Power supply: * VCC = VCCQ = +2.5V 0.2V 184 pin DIMM package * D3 PCB height: 28.58mm (1.125")
NOTE: Consult factory for availability of: * RoHS compliant products * Vendor source control options * Industrial temperature option * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice.
DESCRIPTION
The WV3EG32M64ETSU is a 32Mx64 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM components. The module consists of eight 32Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
OPERATING FREQUENCIES
DDR333 @CL=2.5 Clock Speed CL-tRCD-tRP 166MHz 2.5-3-3
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PIN CONFIGURATION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 SYMBOL VREF DQ0 VSS DQ1 DQS0 DQ2 VCC DQ3 NC NC VSS DQ8 DQ9 DQS1 VCCQ CK1 CK1# VSS DQ10 DQ11 CKE0 VCCQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VCCQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VCC DQ26 DQ27 A2 VSS A1 NC NC VCC PIN 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 SYMBOL NC A0 NC VSS NC BA1 DQ32 VCCQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VCCQ WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 VCC NC DQ48 DQ49 VSS CK2# CK2 VCCQ DQS6 DQ50 DQ51 VSS VCCID DQ56 DQ57 VCC DQS7 DQ58 DQ59 VSS NC SDA SCL PIN 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 SYMBOL VSS DQ4 DQ5 VCCQ DM0 DQ6 DQ7 VSS NC NC NC VCCQ DQ12 DQ13 DM1 VCC DQ14 DQ15 NC VCCQ NC DQ20 A12 VSS DQ21 A11 DM2 VCC DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VCCQ DM3 A3 DQ30 VSS DQ31 NC NC VCCQ CK0 CK0# PIN 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 SYMBOL VSS NC A10 NC VCCQ NC VSS DQ36 DQ37 VCC DM4 DQ38 DQ39 VSS DQ44 RAS# DQ45 VCCQ CS0# NC DM5 VSS DQ46 DQ47 NC VCCQ DQ52 DQ53 NC VCC DM6 DQ54 DQ55 VCCQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VCCQ SA0 SA1 SA2 VCCSPD A0-A12 BA0-BA1 DQ0-DQ63 DQS0-DQS7 CK0, CK1, CK2 CK0#, CK1#, CK2# CKE0 CS0# RAS# CAS# WE# DM0-DM7 VCC VCCQ VSS VREF VCCSPD SDA SCL SA0-SA2 VCCID NC
PIN NAMES
Address input (Multiplexed) Bank Select Address Data Input/Output Data Strobe Input/Output Clock Input Clock Input Clock Enable input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data-in-mask Power Supply Power Supply for DQS Ground Power Supply for Reference Serial EEPROM Power Supply Serial data I/O Serial clock Address in EEPROM VCC Indentification Flag No Connect
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FUNCTIONAL BLOCK DIAGRAM
CS0# DQS0 DM0 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS
DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6
DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
DQS
DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7
DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
DQS
DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
DQS
RAS# CAS# BA0-BA1 WE# A0-A12 CKE0
RAS#: DDR SDRAMs CAS#: DDR SDRAMs BA0-BA1: DDR SDRAMs WE#: DDR SDRAMs A0-A12: DDR SDRAMs CKE0: DDR SDRAMs
SCL WP A0 SA0 SERIAL PD SDA A1 SA1 A2 SA2
*Clock Net Wiring
DRAM 1 1.5PF
R = 120 Ohm Card Edge
DRAM 3 1.5PF 1.5PF DRAM 5 1.5PF
CLOCK INPUT CK0, CK0# CK1, CK1# CK2, CK2# 2 SDRAMS 3 SDRAMS 3 SDRAMS
VCCSPD VCC/VCCQ VREF VSS
SPD DDR SDRAMs DDR SDRAMs DDR SDRAMs
NOTE: All datalines are terminated through a 22 ohm series resistor.
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WV3EG32M64ETSU-D3
ADVANCED
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Voltage on VCCQ supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Symbol VIN, VOUT VCC VCCQ TSTG PD IOS Value -0.5 to 3.6 -1.0 to 3.6 -0.5 to 3.6 -55 to +150 8 50 Units V V V C W mA
Note: Permanent device damage may occur if `ABSOLUTE MAXIMUM RATINGS' are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability
0C TA 70C, VCC = VCCQ = 2.5V 0.2V Parameter Supply voltage (for device with a nominal VCC of 2.5V) I/O Supply voltage I/O Reference voltage I/O Termination voltage(system) Input logic high voltage Input logic low voltage Input Voltage Level, CK and CK# inputs Input Differential Voltage, CK and CK# inputs Input crossing point voltage, CK and CK# inputs Input leakage current Output leakage current Output High Current (Normal strengh driver); VOUT = VTT + 0.84V Output High Current (Normal strengh driver); VOUT = VTT + 0.84V Output High Current (Half strengh driver); VOUT = VTT + 0.84V Output High Current (Half strengh driver); VOUT = VTT + 0.84V Symbol VCC VCCQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VIX(DC) II IOZ IOH IOL IOH IOL Min 2.3 2.3 VCCQ/2 -50mV VREF -0.04 VREF +0.15 -0.3 -0.3 0.36 1.15 -2 -5 -16.8 16.8 -9 9 Max 2.7 2.7 VCCQ/2 +50mV VREF +0.04 VCCQ +0.3 VREF -0.15 VCCQ +0.3 VCCQ +0.6 1.35 2 5 Unit V V V V V V V V uA uA mA mA mA mA Note
DC CHARACTERISTICS
1 2 4 4 3 5
Notes: 1. Includes 25mV margin for DC offset on VREF, and a combined total of 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled to VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of 3nH. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 3. VID is the magnitude of the difference between the input level on CK and the input level on CK#. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VCCQ of the transmitting device and must track variations in the DC level of the same.
CAPACITANCE
TA = 25C, f = 1MHz, VCC = VCCQ = 2.5V Parameter Input Capacitance (A0-A12, BA0-BA1, RAS#, CAS#, WE#) Input Capacitance (CKE0) Input Capacitance (CS0#) Input Capacitance (CLK0, CLK1, CLK2) Input Capacitance (DM0-DM7) Data and DQS input/output capacitance (DQ0-DQ63)
July 2005 Rev. 0 4
Symbol CIN1 CIN2 CIN3 CIN4 CIN5 COUT1
Min 49 42 42 25 6 6
Max 57 50 50 30 7 7
Unit pF pF pF pF pF pF
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0C TA 70C, VCC = VCCQ = 2.5V 0.2V Includes DDR SDRAM component only
WV3EG32M64ETSU-D3
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
Parameter Operating one bank activeprecharge current; Operating one bank activeread-precharge current; Precharge power-down current; Precharge quiet standby current; Precharge standby current; Active power-down current; Active standby current;
Symbol IDD0
Conditions tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address businputs are SWITCHING; Data pattern is same as IDD4W All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputsare STABLE; Data bus inputs are FLOATING All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS - is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRAS-max(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING CK and CK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the following page for detailed timing conditions
DDR333@ CL = 2.5 720
Units mA
IDD1
920
mA
IDD2P IDD2Q IDD2F IDD3P IDD3N
24 160 200 280 440
mA mA mA mA mA
Operating burst write current;
IDD4W
1280
mA
Operating burst read current;
IDD4R
1280
mA
Burst auto refresh current;
IDD5
1360
mA
Self refresh current; Operating bank interleave read current;
IDD6 IDD7
24 2240
mA mA
Note: These specifications apply to modules built with Samsung components only.
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WV3EG32M64ETSU-D3
ADVANCED
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
1. 2. 3. Typical Case : VCC=2.5V, T=25C Worst Case : VCC=2.7V, T=10C Only one bank is accessed with tRC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0mA Timing Patterns : * DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRCD=10*tCK, tRAS=7*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst
IDD7A : OPERATING CURRENT : FOUR BANKS
1. 2. 3. Typical Case : VCC=2.5V, T=25C Worst Case : VCC=2.7V, T=10C Four banks are being interleaved with tRC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA Timing Patterns : * DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst
4.
4.
Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3 R (0-3) = Read Bank 0-3
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DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data into Read command Col. address to Col. address delay Clock cycle time Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time(fast) Address and Control Input hold time(fast) Address and Control Input setup time(slow) Address and Control Input hold time(slow) Data-out high impedence time from CK/CK Data-out low impedence time from CK/CK Output Slew Rate Matching Ratio(rise to fall) Symbol tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tCCD tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH tDQSH tDQSL tDSC tIS tIH tIS tIH tHZ tLZ tSLMR 335 Min 60 72 42 18 18 12 15 1 1 6 0.45 0.45 -0.6 -0.7 -- 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.75 0.75 0.8 0.8 -0.7 0.67 Max Unit ns ns ns ns ns ns ns tCK tCK ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK tCK ns ns ns ns ns ns Note
70K
12 0.55 0.55 +0.6 +0.7 0.45 1.1 0.6 1.25
12
3
1.1
+0.7 +0.7 1.5
5.7~9 5.7~9 6~9 6~9 1 1
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DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (continued)
Parameter Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Power down exit time Exit self refresh to non-Read command Exit self refresh to read command Refresh interval time Output DQS valid window Clock half period Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time Symbol tMRD tDS tDH tIPW tDIPW tPDEX tXSNR tXSRD tREFI tQH tHP tQHS tWPST tRAP tDAL B3 Min 12 0.45 0.45 2.2 1.75 6 75 200 tHP-tQHS tCLmin or tCHmin 0.4 18 (tWR/tCK) + (tRP/tCK) Max Unit ns ns ns ns ns ns ns tCK us ns ns ns tCK tCK Note
8 8
7.8 -- -- 0.55 0.6
4 11 10, 11 11 2 13
AC OPERATING TEST CONDITIONS
VCC = 2.5V, VCCQ = 2.5V, 0C TA 70C Value 0.5 * VCCQ 1.5 VREF+0.31/VREF-0.31 VREF VTT See Load Circuit Parameter Input reference voltage for Clock Input signal maximum peak swing Input Levels (VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Unit V V V V V Note
OUTPUT LOAD CIRCUIT (SSTL_2)
VTT =0.5*VCCQ
RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*VCCQ
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Component Notes 1. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ). The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. For command/address input slew rate: 1.0 V/ns For command/address input slew rate: 0.5 V/ns and 1.0 V/ns For CK & CK# slew rate 1.0 V/ns These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. Slew Rate is measured between VOH(ac) and VOL(ac).
WV3EG32M64ETSU-D3
ADVANCED
2.
10. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces. 11. tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and pchannel to n-channel variation of the output drivers. 12. tDQSQ Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 13. tDAL = (tWR/tCK) + (tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5 clocks
3.
4. 5. 6. 7. 8.
9.
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ORDERING INFORMATION FOR D3
Part Number WV3EG32M64ETSU335D3xG Speed 166MHz/333Mb/s CAS Latency 2.5 tRCD 3 tRP 3 Height* 28.58 (1.125") Temperature 0C to 70C
NOTES: * Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
PACKAGE DIMENSIONS FOR D3
133.35 0.15 (5.25 0.006) 128.95 (5.077") 4.00 (0.158 (2x)) 3.30 (0.130) MAX
17.80 (0.70) 10.00 (0.393) 64.77 (2.550) 1.27 (0.050) 49.53 (1.95)
28.58 0.15 (1.125 0.006)
2.175 (0.085) 1.80 (0.071)
2.30 (0.10) (2x) 3.00 (0.118) (4x)
1.27 0.10 (0.050 0.004)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
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WV3EG32M64ETSU-D3
ADVANCED
PART NUMBERING GUIDE
WV 3 E G 32M 64 E T S U xxx D3 x G
WEDC MEMORY DDR GOLD DEPTH BUS WIDTH x8 TSOP 2.5V UNBUFFERED SPEED (MHz) PACKAGE 184 PIN COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = ROHS COMPLIANT
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Document Title
256MB - 32Mx64 DDR SDRAM UNBUFFERED
WV3EG32M64ETSU-D3
ADVANCED
Revision History Rev #
Rev 0
History
Created
Release Date
7-05
Status
Advanced
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